1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device permitting high-speed access operation at a timing of activation of an address buffer, while reducing a stand-by current consumption.
2. Description of the Background Art
In a memory device in which a data signal is transmitted between a selected memory cell and an outside according to an externally supplied address signal, one known technique to reduce current consumption during stand-by is to provide a transmission circuit at an input stage of an address buffer taking in the address signal that is inactivated during stand-by. Provision of such a transmission circuit can prevent generation of an unnecessary through current within the address buffer.
To relax noise in the address signal and to secure margin for write recovery time in a static random access memory (SRAM), a prescribed delay time is added to the externally supplied address signal in an address buffer circuit, and the resulting address signal is applied to an address decoder performing selection of rows and columns of memory cells.
FIG. 11 is a block diagram illustrating a configuration of a conventional address buffer 500 and peripheral circuits thereof, to be used for these purposes.
Referring to FIG. 11, n+1 bits of address signal A0-An (n is a natural number) are input into address buffer 500, which in turn transmits each bit of the received address signal to an address decoder 560.
Address buffer 500 detects transition in signal level of each bit of the address signal, and transmits the information to a global ATD circuit 570. Global ATD circuit 570 outputs an address transition detecting signal GATD that is activated when the signal level changes in at least one of the bits of the address signal.
Address buffer 500 receives the address signal from address signal input terminals 501-0 to 501-n that are provided corresponding to respective bits of the address signal. Address buffer 500 receives from a node n101 an address buffer activation signal FACT generated by an address buffer activation circuit 550. Address buffer activation circuit 550 activates (to an L level) address buffer activation signal FACT in response to the activation (to an L level) of a chip select signal /CS designating activation of the entire memory device.
Address buffer 500 further includes address signal input circuits 510-0 to 510-n that are provided corresponding to respective bits of the address signal. As each address signal input circuit has the same configuration and operates in the same manner, the configuration of address input circuit 510-0 provided corresponding to a leading bit A0 of the address signal will now be described representatively.
Address input circuit 510-0 includes an address signal transmission circuit 520 that is activated in response to address buffer activation signal FACT. Address signal transmission circuit 520 is a circuit provided for reducing the current consumption of the address buffer during stand-by.
FIG. 12 is a circuit diagram showing a configuration of address signal transmission circuit 520.
Referring to FIG. 12, address signal transmission circuit 520 includes P type MOS transistors Q50, Q51, coupled in series between a power supply line and a node N1, and an N type MOS transistor Q52 coupled between node N1 and a ground line. Transistors Q51 and Q52 have gates connected to address signal input terminal 501-0, and transistor Q50 has a gate connected to node n101.
Address signal transmission circuit 520 further includes an N type MOS transistor Q53 connected between node N1 and the ground line. Transistor Q53 has a gate connected to node n101. With such a configuration, transistor Q53 turns on and transistor Q50 turns off when address buffer activation signal FACT is at an inactive state (of an H level). Thus, address signal A0 is not transmitted to node N1, and the voltage level of node N1 is fixed at a ground voltage GND (at an L level) by transistor Q53.
In contrast, when address buffer activation signal FACT is activated (to an L level), transistor Q53 turns off and transistor Q50 turns on. Thus, node N1 is separated from the ground line, and an inverter formed of transistors Q51 and Q52 to which a current is supplied by transistor Q50 inverts the signal level of address signal A0 and transmits the inverted state to node N1.
The signal level at node N1 is transmitted to node n102 via inverters IV51 and IV52.
With such a configuration, it is possible to cut a through current at address signal transmission circuit 520, regardless of the signal level of address signal A0. Furthermore, since the signal level at node N1 during stand-by can be set in advance, it is also possible to cut the through current at each of post-connected circuits on stand-by without difficulty.
Referring to FIG. 11 again, address signal input circuit 510-0 further includes a delay circuit 530 that outputs to node n106 a change in voltage level at node n102 after a lapse of delay time td, and a local ATD circuit 540 that outputs to node n107 a one-shot pulse that is activated (to an L level) when the voltage level at node n102 changes.
The voltage levels at nodes n106 and n107 are inverted by inverters IV53 and IV56 and transmitted to nodes n103 and n104, respectively. Output to node n103 is a data signal DA0 that corresponds to the signal level of the input address signal. Similarly output to node n104 is a one-shot pulse signal LA0 that is activated (to an H level) when address signal A0 changes from an H level to an L level or from the L level to the H level.
Delay time td is set by delay circuit 530 such that a sufficient time is guaranteed for relaxing noise of the address signal input to the address input terminals, or for securing margin for write recovery time.
Other address signal input circuits 510-1 to 510-n operate in the same manner, and similarly output signals DA1 to DAn and LA1 to LAn. Address decoder 560 generates address select signals AS0 to ASn for selecting an address corresponding to the signal level given to each bit at each of the address signal input terminals.
Global ATD circuit 570 receives outputs LA0 to LAn from respective local ATD circuits and, when at least one of the signals LA0 to LAn is activated, activates address transition detecting signal GATD by adding an appropriate delay time thereto. GATD is a pulse signal activated for a prescribed time period, which detects start of a new access by monitoring switching of the address signal. For example, this signal GATD can be used to control equalization of data lines or the like such that the equalizing operation is completed immediately before the activation timing of word lines. Data reading and writing operations can thus be sped up.
The above-described delay time to be added by global ATD circuit 570 can be adjusted to obtain optimal timing between activation of LA0 to LAn at local ATD circuits and activation of word lines.
Now, another configuration of conventional address buffer will be described, in the case where it has a byte control function that enables portion-by-portion switching between activation and inactivation of a word configuration to be handled.
FIG. 13 is a block diagram showing a configuration of a conventional address buffer having the byte control function and peripheral circuits thereof.
In FIG. 13, the configuration of an address buffer activation circuit 555 is different from that of address buffer activation circuit 550 shown in FIG. 10.
Referring to FIG. 13, address buffer activation circuit 555 receives byte control signals /BC1 and /BC2. The byte control signal is a signal that controls switching between activation and inactivation for every byte, by dividing a word configuration having, for example, 16 bits into 2 bytes of 8 bits each. Each of byte control signals /BC1 and /BC2 is inactivated (to the H level) when the corresponding byte is inactivated.
Address buffer activation circuit 555 includes: a logic circuit 550 that receives a chip select signal /CS and a ground voltage GND as two inputs and outputs a result of their NOR operation to node n301; an inverter IV50 that inverts the signal level of node n301; a logic circuit 562 that receives an output of inverter IV50 and signal /BC1 as its inputs and outputs their NOR operation result; a logic circuit 564 that receives the output of inverter IV50 and signal /BC2 as its inputs and outputs the NOR operation result; and a logic circuit 566 that receives outputs of logic circuits 562 and 564 and outputs their OR operation result.
Address buffer activation circuit 555 further includes a logic gate LG50 that receives outputs of logic circuits 550 and 566 as two inputs and outputs their NAND operation result. The output of logic gate LG50 is transmitted as address buffer activation signal FACT via node n101 to each address input circuit.
With such a configuration, address buffer activation signal FACT recognizes the stand-by state when both byte control signals /BC1 and /BC2 are at an inactive state (at an H level) and when chip select signal /CS is at an inactive state (at an H level), and inactivates the address buffer.
Conversely, if chip select signal /CS is activated and at least one of byte control signals /BC1 and /BC2 is activated (to the L level), i.e., one or more bytes are activated, then it recognizes the active state and activates the address buffer.
Therefore, it is possible to determine activation/inactivation of the address buffer according to a combination of chip select signal /CS and byte control signals /BC1, /BC2.
FIG. 14 is a timing chart illustrating an operation of the address buffer described in conjunction with FIG. 11 and problems that pose.
Referring to FIG. 14, with an access during the time from T0 to T1, address signal A0 is at the L level, and thus, address A(0) is selected.
When chip select signal /CS is activated (to the L level) at time T0, the address buffer activation circuit activates (to the L level) address buffer activation signal FACT after a lapse of time tf, whereby the voltage level of node n10l is changed. In response thereto, the voltage level of node n102 rises to the H level at timing t2, and after a lapse of delay time td, the voltage level of node n106, i.e. the output of delay circuit 530, rises to the H level.
In response thereto, the voltage level of node n103 changes. Address select signal AS0 is set to the H level, while AS1 is set at the L level.
When address signal A0 changes from the L level to the H level at time T1, the voltage level of node n102 changes in response, since address buffer activation signal FACT is already activated. Furthermore, at timing t7 after a lapse of time td, the voltage level of node n106, to which the output of delay circuit 530 is transmitted, changes to the L level.
In response thereto, signal DA0 being output to node n103 rises from the L level to the H level at timing t16. In response, address select signals AS0 and AS1, output by address decoder 560, change to the L level and to the H level, respectively.
Therefore, in the case where an access operation is started with the activation of the address buffer in response to the activation of /CS signal at time T0 (hereinafter, also referred to as "CS access"), a time period from the start of access to the time when the address select signal is output is expressed as "tcs".
In contrast, in the case where the access operation is started by the change of the address signal at time T1 after the address buffer is activated (hereinafter, also referred to as "address access"), a time period from the time when the address signal changes to the time when address select signals AS0 and AS1 respond to the change of the address signal is expressed as "tad".
As seen from FIG. 14, delay time tad in the case of address access is determined by delay time td that is added by delay circuit 530, whereas access time tcs in the case of CS access is determined by the sum of delay time td that is added by delay circuit 530 and time tf that is needed for the address buffer activation circuit to activate signal FACT. Thus, the delay in the case of CS access is greater than that in the case of address access. In other words, an unnecessarily long delay time will be added in the access operation involving activation of the address buffer.
Precharge operation of data lines or the like needs to be completed before the address select signals are set to drive word lines. Therefore, address transition detecting signal GATD is activated during the time period from t22 to t23 before timing t64 when the address select signal is switched, with the change in voltage level at node n102 as a starting point. Likewise, in the case of address access, address transition detecting signal GATD is activated during the time period from t24 to t25 before the address select signals AS0 and AS1 are set.
In the case of CS access, the time period from the activation of /CS signal to the time when address signal transmission circuit 520 is activated and the voltage level of node n102 is changed increases as the number of address bits or wiring resistance and wiring capacitance of node n101 increases. Thus, there has been a problem of reduction in the CS access speed with the increase in the size of the semiconductor memory device to be mounted.
FIG. 15 is a timing chart illustrating the operation of the address buffer shown in FIG. 12 having the byte control function and problem thereof.
Referring to FIG. 15, with an access during the time from T0 to T1, address A0 is at the L level, and thus, address A(0) is selected. With an access during the time from T1 to T2, address A0 is at the H level, and therefore, address A(1) is selected.
Similar to the case of FIG. 14, the address buffer is activated because signal /CS, and also signals /BC1 and /BC2 in this case, are activated at time T0.
However, in the case where the access operation is started with activation of the address buffer in response to the activation of signals /BC1 and /BC2 (hereinafter, also referred to as "BC access"), the voltage level of address buffer activation signal FACT, i.e., the voltage level of node n101, is actually changed at timing t83, time tff later than time T0. At this timing, the address signal is taken into the address input circuit, and the voltage level of node n102 changes.
With this timing as a starting point, the voltage level of each node changes, and at timing t91 after a lapse of delay time td, address select signal AS0 changes from the L level to the H level.
Likewise, address transition detecting signal GATD is activated at a time period from t92 to t93 prior to timing t91, in response to the change in the voltage level of node n102.
In the case of address access that is started after the address buffer has been activated, the voltage level of address signal A0 changes at time T1, and in response, the voltage level of node 102 changes.
Therefore, in this address access, it is possible to set the voltage level of the address select signal relatively quickly. Specifically, address select signal AS1 can be set to the H level at timing t21, only tad later than time T1. Address transition detecting signal GATD is activated during a time period from timing t94 to timing t95 before timing t21, with the change in the voltage level of node n102 as a starting point.
Comparing FIG. 15 with FIG. 14, address buffer activation circuit 555 determines activation of the address buffer activation signal, not according to the signal CS only, but according to the combination of the states of chip select signal CS and byte control signals /BC1 and /BC2. Therefore, it is necessary to provide logic circuits 562, 564 and 566 additionally. It has also been found that the delay time tff from the timing when the setting of these control signals changes to the timing when the address buffer activation signal is actually activated is further increased. Thus, the delay amounts for the CS and BS accesses tend to increase with the increase in the size of the semiconductor memory devices, which hinders speeding of the entire memory device.
Taking only speed into consideration, some countermeasures may be considered, such as giving up control of activation of the address signal transmission circuit by a combination of chip select signal /CS and byte control signals /BC1 and /BC2, and decreasing delay time td being set by delay circuit 530. If these countermeasures are conducted, however, there may arise disadvantages such as an increase in current consumption during stand-by, and a decrease in margin for write recovery time.